Revised Fig 10.78

Corrected Verilog code (original was synchronous):

always @(posedge CLKIN or negedge RESETBAR)
  if (!RESETBAR)
    begin
      Q <= 4'b0000;
      QBAR <= 4'b1111;
    end
  else
    begin
      Q <= D;
      QBAR <= ~D;
    end